Transistor display panel and manufacturing method thereof
US10199405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Aug 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a transistor display panel and a transistor display panel, the method including forming a polycrystalline silicon layer on a substrate; forming an active layer by patterning the polycrystalline silicon layer; forming a first insulating layer covering the substrate and the active layer; exposing the active layer by polishing the first insulating layer using a polishing apparatus; and forming a second insulating layer that contacts the first insulating layer and the active layer, wherein exposing the active layer by polishing the first insulating layer includes coating a first slurry on a surface of the first insulating layer, the first slurry reducing a polishing rate of the active layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.