Transistor and method for forming the same
US10199478B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 29, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Sep 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for forming a transistor, including: forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer; forming a second gate structure on the active layer; forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure; and forming a first interlayer dielectric layer covering the base structure and the second gate structure. The method also includes: forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure; and forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.