Low temperature poly-silicon transistor array substrate and fabrication method thereof, and display device
US10199506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Mar 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6721
Abstract
The embodiments of the present invention disclose a low temperature poly-silicon (LTPS) transistor array substrate and a method of fabricating the same, and a display device. The LTPS transistor array substrate comprises a substrate; a poly-silicon semiconductor active region provided on the substrate; a gate insulated from the poly-silicon semiconductor active region; and a dielectric spacer region provided on a side wall of the gate, wherein a portion of the poly-silicon semiconductor active region corresponding to the dielectric spacer region comprises a buffer region, and the dielectric spacer region surrounds the side wall of the gate and covers the buffer region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.