DTC-based PLL and method for operating the DTC-based PLL
US10200047B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 25, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | May 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.