Patent · US Active

Multi-loop PLL structure for generating an accurate and stable frequency over a wide range of frequencies

US10200049B2 · kind B2 · utility

0Cited by
4References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 5, 2017
Grant dateFeb 5, 2019
Priority date—
Expiry dateJan 8, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L7/185
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A multiloop PLL circuit comprising:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.