Method and apparatus for analog to digital error conversion with multiple symmetric transfer functions
US10200056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2018 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | May 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/60
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two dig…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.