Shift register capable of defending against DPA attack
US10200193B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Aug 28, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Sep 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a shift register capable of defending against DPA attack, comprising 4 master-slave D flip-flops, 12 two-input NAND/AND gates, 4 three-input NOR/OR gates and 40 inverters; the 4 master-slave D flip-flops are provided with reset function; it is based on TSMC 65 mm CMOS technique; as indicated by Spectre simulation verification, the shift register of the present invention has correct logic function with NED and NSD below 2.66% and 0.63% respectively under multi PVT combinations, which is provided with significant performance in defense differential power consumption analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.