Coordination for one-sided memory access in a partitioned global address space
US10200472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2014 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Aug 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/154
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generally, this disclosure provides systems, devices, methods and computer readable media for improved coordination between sender and receiver nodes in a one-sided memory access to a PGAS in a distributed computing environment. The system may include a transceiver module configured to receive a message over a network, the message comprising a data portion and a data size indicator and an offset handler module configured to calculate a destination address from a base address of a memory buffer and an offset counter. The transceiver module may further be configured to write the data portion to the memory buffer at the destination address; and the offset handler module may further be configured to update the offset counter based on the data size indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.