Memory module having error correction logic
US10204008B2 · kind B2 · utility
9Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Apr 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes an error correction logic to provide data error protection for data stored in the memory module. The error correction logic is selectively controllable between an enabled state and a disabled state. Data stored in the memory module is without error protection provided by the memory module if the error correction logic is in the disabled state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.