Memory controller for multi-level system memory with coherency unit
US10204047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2015 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Mar 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.