Memory optimization by phase-dependent data residency
US10204059B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 29, 2016 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide memory optimization by phase-dependent data residency. Application programs are profiled a priori or in real time for temporal memory usage. Memory regions such as initialization data are proactively removed from memory when the application transitions to a new phase. A hypervisor monitors application activity and coordinates the removal of memory regions that are no longer needed by the application. Additionally, memory regions that are anticipated to be needed in the future are proactively preloaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.