Methods and apparatus for a multiple master bus protocol
US10204065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2015 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Feb 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide systems, methods, and apparatus for arbitrating a multi-master computer bus. The embodiments include a multi-master serial computer bus; a first master coupled to the bus; a second master coupled to the bus; a slave device coupled to the bus; a first I/O line from the first master going to the second master and the slave device; and a second I/O line from the second master going to the first master and the slave device. A bus arbitration protocol for arbitrating use of the bus restricts the masters to a single transaction each time either master becomes a bus master, and the masters are each adapted to use the I/O lines to signal to each other not to become a bus master. Numerous other aspects are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.