Memory device with strap cells
US10204660B2 · kind B2 · utility
3Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Dec 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is arranged across the first sub-bank. The second portion is arranged across the second sub-bank, and is coupled to the first portion via the first strap cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.