Double data rate synchronous dynamic random access memory and output driving circuit thereof
US10204676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Sep 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double data rate synchronous dynamic random access memory includes a control circuit and an output driving circuit. The control circuit provides a first voltage, a second voltage, a third voltage and a fourth voltage. The output driving circuit couples to the control circuit and includes a pull-up circuit, a pad and a pull-down circuit. When a voltage of the pad rises from the fourth voltage to the first voltage, a voltage between a drain and a source of a second driving transistor in the pull-down circuit is between the third voltage and the fourth voltage. When a voltage of the pad falls from the first voltage to the fourth voltage, a voltage between a drain and a source of a first driving transistor in the pull-up circuit is between the first voltage and the second voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.