Highly compact non-volatile memory and method thereof
US10204679B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 10, 2016 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Nov 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.