Memory array, and method for reading, programming and erasing memory array
US10204688B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 17, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Aug 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down column is disposed between the two adjacent blocks. Each source pull down column has a plurality of flash memory cells. A source of each flash memory cell in the source pull down column is coupled to sources of the flash memory cells of the plurality memory columns in a same row as the flash memory cell in the source pull down column to pull down a source of a selected flash memory cell to 0 V.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.