Shift register unit, gate drive circuit having the same, and driving method thereof
US10204696B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 8, 2016 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Dec 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application discloses a shift register unit circuit including an input port for receiving an input signal, an output port for outputting a gate driving signal, a first clock input port for receiving a first clock signal, a second clock input port for receiving a second clock signal, a pull-up node, a first pull-down node, a second pull-down node, a pull-up control sub-circuit connected to the input port and the pull-up node, a pull-up sub-circuit connected to the first clock input port and the pull-up node, a pull-down control sub-circuit connected to the first clock input port, a pull-down sub-circuit connected to the first pull-down node and the second pull-down node, a reset sub-circuit receiving a reset signal to control the potential level at the second pull-down node, and an initialization sub-circuit configured to receive an enabling signal for pulling-down the potential level at the second pull-down node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.