Semiconductor device having a multilayer wiring structure
US10204858B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Oct 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.