Self-timed processors implemented with multi-rail null convention logic and unate gates

US10205453B2 · kind B2 · utility

Assignee

• Eta Compute, Inc. · US

Inventors

• Chao Xu · Beijing, CN
• Gopal Raghavan · Thousand Oaks, US
• Ben Wiley Melton · Santa Clara, US
• Vidura Manu Wijayasekara · Thousand Oaks, US
• Bryan Cope · Austin, US
• David Cureton Baker · Austin, US
• John Whitaker Havlicek · Thousand Oaks, US

Key dates

• Filing date: Apr 9, 2018
• Grant date: Feb 12, 2019
• Expiry date: Apr 9, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/177
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.