Pulse width modulation pattern generator circuit, corresponding device and method
US10206258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2018 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | May 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B45/325
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.