Test apparatus and testable asynchronous circuit
US10209299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/25
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are a test apparatus and a testable asynchronous circuit. The test apparatus includes: a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first selector, a second selector, a D flip-flop, and a first output end. The first input end is configured to input a data signal or a test result of a previous circuit under test; the second input end is configured to input a test excitation signal or a test result that is output by a previous test apparatus; the third input end is configured to input a clock signal; the fourth input end is configured to input a selection signal; and the fifth input end is configured to input a selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.