Interface chip and built-in self-test method therefor
US10209302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2016 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Jan 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An interface chip with a built-in self-test mechanism. An electrical physical layer (EPHY) provides a signal to a transmission terminal of the interface chip, and gets a signal from a reception terminal of the interface chip. A digital code generator generates a source code to be scrambled as a scrambled code and then encoded by an encoder and conveyed to the EPHY to be converted into the signal that is provided to the transmission terminal by the EPHY. The EPHY further converts the signal received from the reception terminal into a receiving code to be decoded by a decoder as a decoded code and then descrambled by the descrambler as a restored code. When the transmission terminal is coupled back to the interface chip via the reception terminal, the code checker checks whether the restored code matches the source code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.