Array substrate, liquid crystal display panel and display device
US10209587B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 13, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Sep 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/123
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides an array substrate, including: a base substrate, a plurality of scan lines; a plurality of data lines arranged by intersecting with the plurality of scan lines; a plurality of thin film transistors arranged in a matrix, each thin film transistor includes a gate electrode, an active layer and a drain electrode; a planarization layer covering the gate electrode, the active layer and the drain electrode, a position of the planarization layer corresponding to the drain electrode is provided with a through hole penetrating through the planarization layer, and the drain electrode is located in the through hole; a filling electrode, located in the through hole and connected with the drain electrode and covers the drain electrode; and a pixel electrode, indirectly connected with the drain electrode through the filling electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.