Patent · US Active

Reducing power consumption in a multi-slice computer processor

US10209757B2 · kind B2 · utility

0Cited by

5References

7Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Steven J. Battle · Austin, US
Owen Chiang · Austin, US
Sam Gat-Shang Chu · Round Rock, US
Saiful Islam · Austin, US
Dung Q. Nguyen · Austin, US
David R. Terry · Austin, US
Eula A. Tolentino · Austin, US

Key dates

Filing date	Nov 2, 2017
Grant date	Feb 19, 2019
Priority date	—
Expiry date	Nov 2, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.