Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and branch pattern to generate conditional branch predictor indexes
US10209993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2016 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Apr 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A branch predictor has a block address useable to access a block of instruction bytes of an instruction cache and first/second byte offsets within the block of instruction bytes. Hashing logic hashes a branch pattern and respective first/second address formed from the block address and the respective first/second byte offsets to generate respective first/second indexes. A conditional branch predictor receives the first/second indexes and in response provides respective first/second direction predictions of first/second conditional branch instructions in the block of instruction bytes. In one embodiment, a branch target address cache (BTAC) provides the byte offsets, and the first/second direction predictions are statically associated with first/second target addresses also provided by the BTAC. Alternatively, the byte offsets are predetermined values, and the first/second direction predictions are dynamically associated with the first/second target addresses based on the relative sizes of the byte offsets provided by the BTAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.