Configurable hardware queue management and address translation
US10210095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Aug 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/65
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.