Configurable hardware queue management
US10210106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Mar 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.