Binary multiplier for binary vector factorization
US10210137B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Jul 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/175
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor, including: decode circuitry to decode instructions; a data cache unit including circuitry to cache data for the processor; and an approximate matrix multiplication (AMM) circuit including: a data receptor circuit to receive a weight vector w and an input vector x, both of size N, and a compression regulating parameter n; a factorizer circuit to factorize w into w≅B·s, by computing a binary factorized matrix B of size N×n, and a dictionary vector s of size n; and a binary multiplier circuit to compute w^T x≅(B·s)^T x=s^T(B^T x), the binary multiplier circuit comprising a hardware accelerator circuit to compute an array product B^T x).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.