Shift register unit, driving method, gate driver on array and display device
US10210791B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 13, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Jul 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0407
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit, a driving method, a gate driver on array and a display device. The shift register unit includes: a first clock control circuit, a second clock control circuit, an output control circuit and an output circuit. The first clock control circuit is configured to, under control of a second control signal from a second control signal terminal, a third clock signal from a third clock signal terminal, and a fourth clock signal from a fourth clock signal terminal, alternately output a second clock signal from a second clock signal terminal and a first clock signal from a first clock signal terminal to the output control circuit. The second clock control circuit is configured to alternately output the first clock signal and the second control signal to the output circuit under control of the second control signal, the third clock signal and the fourth clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.