Non-volatile ferroelectric memory device and method of driving the same
US10210921B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2018 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Feb 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a non-volatile ferroelectric memory device including a semiconductor active layer, a plurality of memory cells connected in series on the semiconductor active layer, and a control circuit for performing a read operation and a program operation on the selected memory cell among the plurality of memory cells, each of the memory cells comprising a para-dielectric layer on the semiconductor active layer; a dielectric stack including a ferroelectric layer stacked on the para-dielectric layer and a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer; and a control gate electrode on the ferroelectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.