Field effect transistor structure for reducing contact resistance

US10211205B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brent R. Den Hartog · Rochester, US
• Eric John Lukes · Stewartville, US
• Matthew James Paschal · Rochester, US
• Nghia V. Phan · Rochester, US
• Raymond A. Richetta · Rochester, US
• Patrick L. Rosno · Rochester, US
• Timothy J. Schmerbeck · Mantorville, US
• Dereje G. Yilma · Rochester, US

Key dates

• Filing date: Apr 27, 2016
• Grant date: Feb 19, 2019
• Expiry date: Aug 21, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.