Low cost flash memory fabrication flow based on metal gate process
US10211303B2 · kind B2 · utility
0Cited by
8References
20Claims
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Key dates
| Filing date | Jul 29, 2016 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.