Fail-safe for shared pin
US10211621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2016 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Feb 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H3/20
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.