Techniques for amplifier output voltage limiting
US10211846B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Nov 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45218
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for limiting the output voltage of an amplifier without directly affecting an output current of the amplifier are provided. In an example, an amplifier can include a plurality of amplifier stages configured to receive an input voltage and to provide an output voltage as a function of the input voltage, and a comparator configured to receive a voltage limit and a representation of the output voltage of the amplifier, to adjust current at an input to a first amplifier stage of the plurality of amplifier stages when the output voltage violates the voltage limit, and to clamp the output voltage at an offset from the voltage limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.