Cooperative triggering
US10216616B2 · kind B2 · utility
1Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2016 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Mar 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is disclosed and comprises a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.