Patent · US Active

Detecting process variation of memory cells

US10217743B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Akshay Kumar · Gothan, IN
Saikat Kumar Banik · Noida, IN

Key dates

Filing date	Feb 16, 2017
Grant date	Feb 26, 2019
Priority date	—
Expiry date	Feb 21, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5004
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having a memory cell array disposed in a first area of the integrated circuit. The memory cell array may include memory cells with first transistors of multiple types. The integrated circuit may include a process sensor disposed in a second area of the integrated circuit that is different than the first area. The process sensor may include a process detector having second transistors of the multiple types that are separate from the first transistors. The second transistors of the process detector may be arranged for detecting process variation of the memory cells of the memory cell array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.