Array substrate and manufacturing method thereof
US10217778B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 15, 2016 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention provides an array substrate and a manufacturing method thereof. The method includes covering a reduction metal layer on an oxide semiconductor layer film and simultaneously forming a source pattern, a drain pattern, a pixel electrode pattern, and an oxide semiconductor layer through patterning the oxide semiconductor layer film and the reduction metal layer with one mask-based operation, followed by reducing the source pattern, the drain pattern, and the pixel electrode pattern to conductors through laser annealing to simultaneously form a source electrode, a drain electrode, and a pixel electrode. The entire manufacturing process needs, at most, only three rounds of mask-based operations so that, compared to the prior art, the number of mask-based operations required can be effectively reduced, the manufacturing operation can be simplified, and the performance of a TFT can be improved and an aperture ratio of the array substrate can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.