Scalable interleaved digital-to-time converter circuit for clock generation
US10218379B2 · kind B2 · utility
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7References
20Claims
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Key dates
| Filing date | Apr 3, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Apr 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.