Methods and apparatus for performing variable and breakout Reed Solomon encoding
US10218386B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2016 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Apr 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/159
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Reed-Solomon encoder that supports multiple code words is provided. The encoder circuit may include partial syndrome calculation circuitry, three matrix multiplication circuits, and two adder circuits. The partial syndrome calculation circuitry may receive a message and generate partial syndromes. The first matrix multiplication circuit may multiply a lower portion of the partial syndromes by a small Lagrange matrix to produce a small parity symbol vector. The second matrix multiplication circuit may multiply the small parity symbol vector by a Vandermonde matrix to produce a product vector. The first adder circuit may add the product vector to an upper portion of the partial syndromes to produce a sum vector. The third matrix multiplication circuit may multiply the sum vector by a large Lagrange matrix to produce a large product vector. The large product vector may be selectively combined with the small parity symbol vector to generate final parity check symbols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.