Instruction and logic to expose error domain topology to facilitate failure isolation in a processor
US10223187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2016 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Aug 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.