Patent · US Active

Graphics processing microprocessor system having a master device communicate with a slave device

US10223288B2 · kind B2 · utility

1Cited by

26References

23Claims

0Family size

Assignee

ARM Norway AS · NO

Inventors

Jorn Nystad · Trondheim, NO
Edvard Sorgard · Trondheim, NO
Borgar Ljosland · Trondheim, NO
Mario Blazevic · Lena, NO

Key dates

Filing date	Jul 15, 2015
Grant date	Mar 5, 2019
Priority date	—
Expiry date	Jul 15, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/1052
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A slave device communicates with a host system via a host communications bus. The host system includes one processor that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processor and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.