Static modelling of an electronic device
US10223486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2013 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | May 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design verification system verifies an electronic device design based on a static model of the electronic device. The static model is an expression of the relationships between modules of the electronic device design and relationships between the behaviors of those modules that can be expressed as set of logical relationships. The static model does not rely on a time variable, but instead reflects a fixed set of relationships between the electronic device modules and between behaviors of the electronic device modules. The static model can be employed by a solver, that identifies whether or how the mathematical relationships of the static model can be reconciled, given a set of constraints. The solver results can be analyzed to identify whether there are errors in the device design, such as resource conflicts, failure of the design to achieve a desired configuration, and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.