Shielded and packaged electronic devices, electronic assemblies, and methods
US10224255B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2016 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Jan 14, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. The electronic assemblies include a printed circuit board with a board surface and a plurality of electrically conductive board pads arranged on the board surface, the shielded and packaged electronic device, and an underfill dielectric layer. The methods include methods of manufacturing the electronic assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.