Semiconductor device
US10224331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2018 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Mar 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/959
Abstract
Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.