Array substrate including vertical TFT, and manufacturing method thereof
US10224406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2016 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Mar 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1368
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A TFT array substrate includes a glass substrate, a buffer layer on the glass substrate, a source electrode, a passivation layer on the buffer layer, a gate electrode on the passivation layer, a gate insulating layer on the passivation layer and the gate electrode, an active layer, and a pixel electrode on the gate insulating layer and the active layer. A first source hole is formed in the buffer layer. The source electrode is disposed in the first source hole. A second source hole is formed in the passivation layer and over the first source hole. The source electrode extends into the second source hole. An active layer mounting hole is formed in the gate insulating layer and over the second source hole. The active layer is in the active layer mounting hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.