Patent · US Active

Apparatus and method for security in an integrated circuit

US10228415B1 · kind B1 · utility

2Cited by

0References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Wei Yee Koay · Kampung Bukit Kechil, MY
Ting Lu · Austin, US
Ka Bo Wong · Bayan Lepas, MY
Rajiv Kumar · Hyderabad, IN

Key dates

Filing date	Sep 27, 2016
Grant date	Mar 12, 2019
Priority date	—
Expiry date	Aug 24, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K17/223
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Test circuitry for providing security in an integrated circuit includes a control circuit and a test power-on-reset circuit. The control circuit determines whether the integrated circuit is configured in a non-secure condition, and that generates a control signal in response to the non-secure condition. Accordingly, the test power-on-reset circuit selectively disables a power-on-reset circuit on the integrated circuit in response the control signal during test operations. The test power-on-reset circuit receives control instructions from the control circuit, and produces a test power-on-reset output according to the control instructions. The integrated circuit includes a logic gate that receives the test power-on-reset output and a power-on-reset signal from the power-on-reset circuit and generates an output signal for bypassing operations of the power-on-reset circuit on the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.