Reset isolation for an embedded safety island in a system on a chip
US10228736B2 · kind B2 · utility
2Cited by
0References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Jan 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The reset isolation mechanism describes an embedded safety island inside a system on a chip which reduces the overall system cost while achieving functional safety. The safety island ensures an orderly shutdown of all or part of the rest of the system on a chip without the possibility of a safety island hang due to incomplete transactions at the time of the reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.