Non-volatile memory repair circuit
US10229025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Nov 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.