Unified paging scheme for dense and sparse translation tables on flash storage systems
US10229048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2016 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Jun 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a first translation table entry for a logical block, map the first translation table entry to a first dump unit, the first dump unit included in an array of dump units, identify a second translation table entry for the logical block in the first dump unit, the second translation table entry also being stored in a storage device, and generate a linked list in the storage device from the second translation table entry associated with the first dump unit, the linked list identifying previous translation table entries associated with the logical block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.