Wiring structures and semiconductor devices
US10229876B2 · kind B2 · utility
7Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2016 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Mar 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.